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zichen1918

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電梯直達

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發(fā)表于 2020-05-06 13:52 |只看該作者 |倒序瀏覽

五一期間我好好拆卸了一下老爺機，我去掉一顆cpu，之前的錯誤log沒有再出現(xiàn)：
0> <00> Memory Stack Test
0>    ERROR: CPU Slave 2 Timeout
0>    WARNING: Unable to dispatch Int to mid 00000002
0>    WARNING: Unable to dispatch Int to mid 00000002
0>    WARNING: Unable to dispatch Int to mid 00000002

我又調(diào)整兩顆cpu的順序，錯誤log再次出現(xiàn)，我覺得很可能是主板cpu的槽位那里出了問題；

對于內(nèi)存相關(guān)的異常log，我將16根內(nèi)存重新分組插了一遍，發(fā)現(xiàn)有一組內(nèi)存報錯，具體哪根不能確定，沒辦法，拆了這組，內(nèi)存報錯也沒再出現(xiàn)：
0>    Unexpected event occurred - Trap
2> <00> DMMU TLB Tag Access Test
0>    tl  tt  tstate          tpc             tnpc
0>    01  30  00000099.80001604  ffffffff.f00b0b98  ffffffff.f00b0b9c
0>    DMMU SFSR 00000000.0058043f
0>    DMMU SFAR 00000000.00000000
0>    (FV)  Fault Valid Bit Set
0>    (OW)  Overwrite Bit Set
0>    (ASI) 0x58
0>    (FT)  Ill LDA/STA ASI, VA, RW size
0>    (CT)  Context 3
0>    (PR)  Privilege Bit Set
0>    (W) Write Bit Set
0>    AFSR 00000000.00100000
0>    AFAR 00000000.08560000
0>    (CE) Correctable ECC Error
0>    SDBH = 00000000.000001f1 SDBL = 00000000.00000031
0>
      Failing address in SIMM Pair 0, SIMM 0

目前最新log如下：
Hardware Power ON
Master CPU online
Master Version: 0000.0000.1700.11a0
Slave  Version: 0000.0000.1700.11a0
CPU E$ (M) 0000.0000.0040.0000 (S) 0000.0000.0040.0000
tton Power ON
Master CPU online
Master Version: 0000.0000.1700.11a0
Slave  Version: 0000.0000.1700.11a0
CPU E$ (M) 0000.0000.0040.0000 (S) 0000.0000.0040.0000

Probing keyboard Done
%o0 = 0000.0000.0054.4001

Executing Power On SelfTest

0>
0>@(#) Sun Ultra 60(UltraSPARC-II 2-way) UPA/PCI POST 2.0.2 10/19/1998 10:46 AM
0>INFO: Processor 0 is master.
0>
0> <00> Init System BSS
0> <00> NVRAM Battery Detect Test
0>STATUS =FAILED
0>TEST =NVRAM Battery Detect
TTF =0
PASSES =1
ERRORS =1
SUSPECT=NVRAM U2706
0>MESSAGE=NVRAM Low Battery
      addr 000001ff.f1001ff0
      exp  00
      obs  10
0> <00> DMMU TLB Tag Access Test
0> <00> DMMU TLB RAM Access Test
0> <00> IMMU TLB Tag Access Test
0> <00> IMMU TLB RAM Access Test
0> <00> Probe Ecache
0>INFO: CPU 450 MHz: 4096KB Ecache
0> <00> Ecache RAM Addr Test
0> <00> Ecache Tag Addr Test
0> <00> Ecache Tag Test
0> <00> Invalidate Ecache Tags
0>INFO: Processor 2 - UltraSPARC-II.
0> <00> Init SC Regs
0> <00> SC Address Reg Test
0> <00> SC Reg Index Test
0> <00> SC Regs Test
0> <00> SC Dtag RAM Addr Test
0> <00> SC Cache Size Init
0> <00> SC Dtag RAM Data Test
0> <00> SC Dtag Init
0> <00> Probe Memory
0>INFO: 512MB Bank 0
0>INFO: 0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> Malloc Post Memory
0> <00> Init Post Memory
0> <00> Post Memory Addr Test
0> <00> Map PROM/STACK/NVRAM in DMMU
0> <00> Memory Stack Test
0>    ERROR: CPU Slave 2 Timeout
0>    WARNING: Unable to dispatch Int to mid 00000002
0>    WARNING: Unable to dispatch Int to mid 00000002
0>    WARNING: Unable to dispatch Int to mid 00000002
0> <00> DMMU Hit/Miss Test
0> <00> IMMU Hit/Miss Test
0> <00> DMMU Little Endian Test
0> <00> IU ASI Access Test
0> <00> FPU ASI Access Test
0> <1f> Init Psycho
0> <1f> PIO Read Error, Master **rt Test
0> <1f> PIO Read Error, Target **rt Test
0> <1f> PIO Write Error, Master **rt Test
0> <1f> PIO Write Error, Target **rt Test
0> <1f> Timer Increment Test
0> <00> Copy Post to Memory
0> <00> Ecache Thrash Test
0> <00> Init Memory
0> <00> Memory Addr w/ Ecache Test
0>INFO: 512MB Bank 0
0>INFO: 0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> Block Memory Addr Test
0>INFO: 512MB Bank 0
0>INFO: 0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> ECC Memory Addr Test
0>INFO: 512MB Bank 0
0>INFO: 0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> Memory Status Test
0>INFO: 512MB Bank 0
0>INFO: 0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> V9 Instruction Test
0> <00> CPU Tick and Tick Compare Reg Test
0> <00> CPU Soft Trap Test
0> <00> CPU Softint Reg and Int Test
0> <1f> Init Psycho
0> <1f> Psycho Cntl and UPA Reg Test
0> <1f> Psycho DMA Scoreboard Reg Test
0> <1f> Psycho Perf Cntl Reg Test
0> <1f> PIO Decoder and BCT Test
0> <1f> PCI Byte Enable Test
0> <1f> Counter/Timer Limit Regs Test
0> <1f> Timer Reload Test
0> <1f> Timer Periodic Test
0> <1f> Mondo Int Map (short) Reg Test
0> <1f> Mondo Int Set/Clr Reg Test
0> <1f> Psycho IOMMU Regs Test
0> <1f> Psycho IOMMU RAM Address Test
0> <1f> Psycho IOMMU CAM Address Test
0> <1f> IOMMU TLB Compare Test
0> <1f> IOMMU TLB Flush Test
0> <1f> Stream Buff A Control Reg Test
0> <1f> Psycho ScacheA Page Tag Addr Test
0> <1f> Psycho ScacheA Line Tag Addr Test
0> <1f> Psycho ScacheA RAM Addr Test
0> <1f> Psycho ScacheA Error Status NTA Test
0> <1f> Psycho ScacheB Page Tag Addr Test
0> <1f> Psycho ScacheB Line Tag Addr Test
0> <1f> Psycho ScacheB RAM Addr Test
0> <1f> Psycho ScacheB Error Status NTA Test
0> <1f> PBMA PCI Config Space Regs Test
0> <1f> PBMA Control/Status Reg Test
0> <1f> PBMA Diag Reg Test
0> <1f> PBMB PCI Config Space Regs Test
0> <1f> PBMB Control/Status Reg Test
0> <1f> PBMB Diag Reg Test
0> <00> FPU Regs Test
0> <00> FPU Move Regs Test
0> <00> FPU State Reg Test
0> <00> FPU Functional Test
0> <00> FPU Trap Test
0> <00> DMMU Primary Context Reg Test
0> <00> DMMU Secondary Context Reg Test
0> <00> DMMU TSB Reg Test
0> <00> DMMU Tag Access Reg Test
0> <00> DMMU VA Watchpoint Reg Test
0> <00> DMMU PA Watchpoint Reg Test
0> <00> IMMU TSB Reg Test
0> <00> IMMU Tag Access Reg Test
0> <00> DMMU TLB Tag Access Test
0> <00> DMMU TLB RAM Access Test
0> <00> Dcache RAM Test
0> <00> Dcache Tag Test
0> <00> Icache RAM Test
0> <00> Icache Tag Test
0> <00> Icache Next Test
0> <00> Icache Predecode Test
0> <00> CPU Addr Align Trap Test
0> <00> DMMU Access Priv Page Test
0> <00> DMMU Write Protected Page Test
0> <1f> Init Psycho
0> <1f> Pri CE ECC Error Test
0> <1f> Pri UE ECC Error Test
0> <1f> Pri 2 bit w/ bit hole UE ECC Err Test
0> <1f> Pri 3 bit UE ECC Err Test
0> <1f> Streaming DMA UE ECC Rd Err Ebus Test
0> <1f> Streaming DMA CE ECC Rd Err Ebus Test
0> <1f> Streaming DMA CE ECC Rd Err Lpbk Test
0> <1f> Consistent DMA UE ECC Rd Error Ebus Test
0> <1f> Consistent DMA UE ECC R/M/W Err Ebus Test
0> <1f> Consistent DMA UE ECC R/M/W Err Lpbk Test
0> <1f> Consistent DMA CE ECC Rd Err Ebus Test
0> <1f> Consistent DMA CE ECC Rd Err Lpbk Test
0> <1f> Consistent DMA CE ECC R/M/W Err Ebus Test
0> <1f> Consistent DMA CE ECC R/M/W Err Lpbk Test
0> <1f> Consistent DMA Wr Data Parity Err Lpbk Test
0> <1f> Pass-Thru DMA UE ECC Rd Err Ebus Test
0> <1f> Pass-Thru DMA UE ECC R/M/W Err Ebus Test
0> <1f> Pass-Thru DMA UE ECC R/M/W Err Lpbk Test
0> <1f> Pass-Thru DMA CE ECC Rd Err Ebus Test
0> <1f> Pass-Thru DMA CE ECC Rd Err Lpbk Test
0> <1f> Pass-Thru DMA CE ECC R/M/W Err Ebus Test
0> <1f> Pass-Thru DMA CE ECC R/M/W Err Lpbk Test
0> <1f> Pass-Thru DMA Write Data Parity Err, Lpbk Test
0> <1f> Init Psycho
0> <1f> Mondo Generate Interrupt Test
0> <1f> Timer Interrupt Test
0> <1f> Timer Interrupt w/ periodic Test
0> <1f> Psycho Stream Buff A Flush Sync Test
0> <1f> Psycho Stream Buff B Flush Sync Test
0> <1f> Psycho Stream Buff A Flush Invalidate Test
0> <1f> Psycho Stream Buff B Flush Invalidate Test
0> <1f> Psycho Merge Buffer w/ Scache A Test
0> <1f> Psycho Merge Buffer w/ Scache B Test
0> <1f> Consist DMA Rd, IOMMU miss Ebus Test
0> <1f> Consist DMA Rd, IOMMU miss Lpbk Test
0> <1f> Consist DMA Rd, IOMMU hit Ebus Test
0> <1f> Consist DMA Rd, IOMMU hit Lpbk Test
0> <1f> Consist DMA Wr, IOMMU miss Ebus Test
0> <1f> Consist DMA Wr, IOMMU miss Lpbk Test
0> <1f> Consist DMA Wr, IOMMU hit Ebus Test
0> <1f> Consist DMA Wr, IOMMU hit Lpbk Test
0> <1f> Stream DMA Rd, IOMMU miss, Scache Miss Ebus Test
0> <1f> Stream DMA Rd, IOMMU miss, Scache Miss Lpbk Test
0> <1f> Stream DMA Rd, IOMMU hit, Scache Miss Ebus Test
0> <1f> Stream DMA Rd, IOMMU hit, Scache Miss Lpbk Test
0> <1f> Stream DMA Rd, IOMMU Miss, Scache(prev rd) Hit Ebus Test
0> <1f> Stream DMA Rd, IOMMU Miss, Scache Hit (prev rd) Lpbk Test
0> <1f> Stream DMA Rd, IOMMU Hit, Scache Hit Ebus Test
0> <1f> Stream DMA Rd, IOMMU Hit, Scache Hit (prev rd) Lpbk Test
0> <1f> Stream DMA Rd, IOMMU Miss, Scache Hit(prev wr) Ebus Test
0> <1f> Stream DMA Rd, IOMMU Miss, Scache Hit (prev wr) Lpbk Test
0> <1f> Stream DMA Rd, IOMMU Hit, Scache Hit(prev wr) Ebus Test
0> <1f> Stream DMA Rd, IOMMU Hit, Scache Hit (prev wr) Lpbk Test
0> <1f> Stream DMA Wr, IOMMU miss, Scache Miss Ebus Test
0> <1f> Stream DMA Wr, IOMMU miss, Scache Miss Lpbk Test
0> <1f> Stream DMA Wr, IOMMU hit, Scache Miss Ebus Test
0> <1f> Stream DMA Wr, IOMMU hit, Scache Miss Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev rd) Hit Ebus Test
0> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev rd) Hit Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev rd) Hit Ebus Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev rd) Hit Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev wr) Hit Ebus Test
0> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev wr) Hit Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev wr) Hit Ebus Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev wr) Hit Lpbk Test
0> <1f> Pass-Thru DMA Rd, Ebus device Test
0> <1f> Pass-Thru DMA Rd, Loopback Mode Test
0> <1f> Pass-Thru DMA Wr, Ebus device Test
0> <1f> Pass-Thru DMA Wr, Loopback Mode Test
0> <1f> Consist DMA Rd, IOMMU LRU Lock Ebus Test
0> <1f> Consist DMA Rd, IOMMU LRU Lock Lpbk Test
0> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache LRU Lock Ebus Test
0> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Rd, IOMMU miss, Scache LRU Lock Ebus Test
0> <1f> Stream DMA Rd, IOMMU Miss, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Rd, IOMMU Hit, Scache LRU Lock Ebus Test
0> <1f> Stream DMA Rd, IOMMU Hit, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache Miss Ebus Test
0> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache Miss Lpbk Test
0> <1f> Consist DMA Wr, IOMMU LRU Locked Ebus Test
0> <1f> Consist DMA Wr, IOMMU LRU Lock Lpbk Test
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache LRU Lock Ebus Test
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Miss, Scache LRU Lock Ebus Test
0> <1f> Stream DMA Wr, IOMMU Miss, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache LRU Lock Ebus Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache Miss Ebus Test
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache Miss Lpbk Test
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache(prev rd) Hit Ebus Test
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache(prev rd) Hit Lpbk Test
0> <00> Init Memory
0>INFO: 512MB Bank 0
0>INFO: 0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> Memory w/ Ecache Test
0>INFO: 512MB Bank 0
0>INFO: 0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> Block Memory Test
0>INFO: 512MB Bank 0
0>INFO: 0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> ECC Blk Memory Test
0>INFO: 512MB Bank 0
0>INFO: 0MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> UltraSPARC-2 Prefetch Instructions Test
0> <00> Test 0: prefetch_mr
0> <00> Test 1: prefetch to non-cacheable page
0> <00> Test 2: prefetch to page with dmmu misss
0> <00> Test 3: prefetch miss does not check alignment
0> <00> Test 4: prefetcha with asi 0x4c is noped
0> <00> Test 5: prefetcha with asi 0x54 is noped
0> <00> Test 6: prefetcha with asi 0x6e is noped
0> <00> Test 7: prefetcha with asi 0x76 is noped
0> <00> Test 8: prefetch with fcn 5
0> <00> Test 9: prefetch with fcn 2
0> <00> Test 10: prefetch with fcn 12
0> <00> Test 11: prefetch with fcn 16 is noped
0> <00> Test 12: prefetch with fcn 29 is noped
0> <00> Test 13: prefetcha with asi 0x15 is noped
0> <00> Test 14: prefetch with fcn 3
0> <00> Test 15: prefetcha14 with fcn 2
0> <00> Test 16: prefetcha80_mr
0> <00> Test 17: prefetcha81_1r
0> <00> Test 18: prefetcha10_mw
0> <00> Test 19: prefetcha80_17 is noped
0> <00> Test 20: prefetcha10_6: illegal instruction trap
0> <00> Test 21: prefetcha11_1w
0> <00> Test 22: prefetcha81_31
0> <00> Test 23: prefetcha11_15: illegal instruction trap
0>STATUS =FAILED  :  First failing device is NVRAM U2706.

Power On Selftest Completed
Status  = 0000.0000.0000.0001 ffff.ffff.f00b.3818 ff9d.ffff.0bd1.e111
ftware Power ON
Master CPU online
Master Version: 0000.0000.1700.11a0
Slave  Version: 0000.0000.1700.11a0
CPU E$ (M) 0000.0000.0040.0000 (S) 0000.0000.0040.0000

@(#) UPA/PCI 3.23 Version 1 created 1999/07/16 12:08
Clearing DTAGS  Done
Probing Memory Done
MEM BASE = 0000.0000.a000.0000
MEM SIZE = 0000.0000.2000.0000
MMUs ON
Copy Done
PC = 0000.01ff.f000.2800
PC = 0000.0000.0000.2844
Decompressing into Memory Done
Size = 0000.0000.0006.eb80
ttya initialized
SC Control: EWP:0 IAP:0 FATAL:0 WAKEUP:0 BXIR:0 BPOR:0 SXIR:0 SPOR:1 POR:0
Starting real time clock...
Incorrect configuration checksum;
Setting NVRAM parameters to default values.
Setting diag-switch? NVRAM parameter to true
Probing Memory Bank #0 128 128 128 128 : 512 Megabytes
Probing Memory Bank #1 0 0 0 0 : 0 Megabytes
Probing Memory Bank #2 128 128 128 128 : 512 Megabytes
Probing Memory Bank #3 128 128 128 128 : 512 Megabytes
Probing Floppy: drive detected on ID0
Probing EBUS SUNW,CS4231
Probing UPA Slot at 1e,0 Nothing there
Probing UPA Slot at 1d,0 SUNW,ffb
Probing /pci@1f,4000 at Device 1  pci108e,1000 network
Probing /pci@1f,4000 at Device 3  scsi disk tape scsi disk tape
Probing /pci@1f,4000 at Device 2  Nothing there
Probing /pci@1f,4000 at Device 4  Nothing there
Probing /pci@1f,4000 at Device 5  Nothing there
Probing /pci@1f,2000 at Device 1  Nothing there
SC Control: EWP:0 IAP:0 FATAL:0 WAKEUP:0 BXIR:0 BPOR:0 SXIR:0 SPOR:1 POR:0
Starting real time clock...
Incorrect configuration checksum;
Setting NVRAM parameters to default values.
Setting diag-switch? NVRAM parameter to true
Probing Memory Bank #0 128 128 128 128 : 512 Megabytes
Probing Memory Bank #1 0 0 0 0 : 0 Megabytes
Probing Memory Bank #2 128 128 128 128 : 512 Megabytes
Probing Memory Bank #3 128 128 128 128 : 512 Megabytes
Probing Floppy: drive detected on ID0
Probing EBUS SUNW,CS4231
Probing UPA Slot at 1e,0 Nothing there
Probing UPA Slot at 1d,0 SUNW,ffb
Probing /pci@1f,4000 at Device 1  pci108e,1000 network
Probing /pci@1f,4000 at Device 3  scsi disk tape scsi disk tape
Probing /pci@1f,4000 at Device 2  Nothing there
Probing /pci@1f,4000 at Device 4  Nothing there
Probing /pci@1f,4000 at Device 5  Nothing there
Probing /pci@1f,2000 at Device 1  Nothing there

(2 X UltraSPARC-II 450MHz), No Keyboard
OpenBoot 3.23, 1536 MB memory installed, Serial #15728639.
Ethernet address ff:ef:ff:ff:ff:ef, Host ID: ffefffff.

The IDPROM contents are invalid

Power On Self Test Failed.  Cause: NVRAM U2706
{0} ok

cpu報錯是因為我又插上了第二顆cpu；我嘗試在ok模式下通過boot disk啟動系統(tǒng)，
Boot device: /***@1f,4000/***@3/***@1,0 File and args: 停留在這里很久沒變化

不知道該怎么辦了......

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zichen1918

白手起家

論壇徽章:: 0

2樓 [報告]

發(fā)表于 2020-05-06 15:48 |只看該作者

今天一直查sun ultra60手冊，根據(jù)日志信息，NVRAM可能是沒電了，需要更換；看到網(wǎng)上有信息說可以再編程，不知道可不可行；有沒有人遇到此類問題呢？

實戰(zhàn)分享：從技術(shù)角度談機器學習入門| 【大話IT】RadonDB低門檻向MySQL集群下戰(zhàn)書 | ChinaUnix打賞功能已上線！ | 新一代分布式關(guān)系型數(shù)據(jù)庫RadonDB知多少？

nimysun

版主

論壇徽章:: 7

操作系統(tǒng)版塊每日發(fā)帖之星
日期:2016-06-05 06:20:00

15-16賽季CBA聯(lián)賽之吉林
日期:2016-06-20 08:24:05

15-16賽季CBA聯(lián)賽之四川
日期:2016-08-18 15:02:02

3樓 [報告]

發(fā)表于 2020-05-08 10:00 |只看該作者

回復(fù) 2# zichen1918

  這個工作站確實夠老的，很多人估計都把相關(guān)的技術(shù)都給忘掉了。
  能給到您的建議就是用最小化CPU內(nèi)存的硬件配置測試一下所有的CPU和內(nèi)存是否都正常工作。
另，nvram是存儲bios的配置的，所以主板電池沒有電的話，是不會影響系統(tǒng)啟動的。
  我覺得您是多個問題在這里。

  首先是主板內(nèi)存CPU可能存在硬件問題，注意那個u2706，我不知道是否是指的是一個內(nèi)存插槽，或者內(nèi)存。

  第二個是硬盤啟動問題，我覺得這個是你的硬盤本身的問題，建議從其他硬盤或者光驅(qū)引導(dǎo)一下�？纯催@個硬盤是否有問題。

  此外這個版真是蕭條了，難得有新帖子。

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zichen1918

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論壇徽章:: 0

4樓 [報告]

發(fā)表于 2020-05-08 15:31 |只看該作者

好，收到，我之前經(jīng)�？吹綎|方蜘蛛，現(xiàn)在都看不到了；
上次搬家，嫌機器太重，就用拉車走了前后單元樓的距離，可能給顛簸壞了；
我五一期間進行的測試，內(nèi)存之前是2G，拆到一組，目前1.5G，已經(jīng)看不到內(nèi)存報錯了；兩顆cpu都切換過槽位，只有一個槽位可以啟動系統(tǒng)；我不確認u60是否第二個cpu槽位能單獨啟動；
u2706 我查過u60的手冊，這是nvram那個芯片，芯片背面寫的是u2706；我覺得你說的硬盤啟動問題有道理，估計硬盤也出問題了，我周末用光盤啟動一下試試；這個家搬的好心疼。