Netra240無法啟動

ching00086

SC Alert: Host System has Reset

SC Alert: CRITICAL ALARM is set

NOTICE: Keyswitch set to diagnostic position.
@(#)OBP 4.22.33 2007/06/18 12:45 Sun Fire V210/V240,Netra 210/240
Clearing TLBs
Power-On Reset
Executing Power On Self Test
0>
0>@(#)Sun Fire[TM] V210/V240,Netra[TM] 210/240 POST 4.22.33 2007/06/18 13:07
       /export/delivery/delivery/4.22/4.22.33/post4.22.x/Fiesta/enxs/integrated  (root)  
0>Copyright 2007 Sun Microsystems, Inc. All rights reserved
0>Hard Powerup RST thru SW
0>OBP->POST Call with %o0=00001000.01014000.
0>Diag level set to MAX.
0>Verbosity level set to MAX.
0>MFG scrpt mode set NORM
0>I/O port set to TTYA.
0>Start Selftest.....
0>CPUs present in system: 0 1
0>Test CPU(s).....
0>Init SB
0>Initialize I2C Controller
0>Init CPU
0>DMMU
0>DMMU TLB DATA RAM Access
0>DMMU TLB TAGS Access
0>IMMU Registers Access
0>IMMU TLB DATA RAM Access
0>IMMU TLB TAGS Access
0>Init mmu regs
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0>        Size = 00000000.00100000...
0>L2 Cache Tags Test
0>Scrub and Setup L2 Cache
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Test  Mailbox
0>Scrub Mailbox
0>CPU Tick and Tick Compare Registers Test
0>CPU Stick and Stick Compare Registers Test
0>Set Timing
0>        UltraSPARC[TM] IIIi, Version 3.4
1>Init CPU
1>        UltraSPARC[TM] IIIi, Version 3.4
1>DMMU
1>DMMU TLB DATA RAM Access
1>DMMU TLB TAGS Access
1>IMMU Registers Access
1>IMMU TLB DATA RAM Access
1>IMMU TLB TAGS Access
1>Init mmu regs
1>Setup L2 Cache
1>L2 Cache Control = 00000000.00f04400
1>        Size = 00000000.00100000...
1>L2 Cache Tags Test
1>Scrub and Setup L2 Cache
1>Setup and Enable DMMU
1>Setup DMMU Miss Handler
1>Test  Mailbox
1>Scrub Mailbox
1>CPU Tick and Tick Compare Registers Test
1>CPU Stick and Stick Compare Registers Test
0>Interrupt Crosscall.....
1>Setup Int Handlers
0>Setup Int Handlers
0>Send Int CPU 1
1>Send Int to Master CPU
0>MB:        Part-Dash-Rev#:  3753484-03-50        Serial#:  1X0GKC
0>CPU0 MB/P0/B0/D0:
0>Part#:  M3 12L2920DZ3-CB3   Serial#:  520238db  Date Code:  0814  Rev#:  3344
0>CPU0 MB/P0/B0/D1:
0>Part#:  M3 12L2920DZ3-CB3   Serial#:  520238de  Date Code:  0814  Rev#:  3344
0>CPU1 MB/P1/B0/D0:
0>Part#:  M3 12L2920DZ3-CB3   Serial#:  5208bfe6  Date Code:  0833  Rev#:  3344
0>CPU1 MB/P1/B0/D1:
0>Part#:  M3 12L2920DZ3-CB3   Serial#:  5208c065  Date Code:  0833  Rev#:  3344
0>Set CPU/System Speed
0>Jumper data = 3a
0>..
0>Send MC Timing CPU 1
0>Init Memory.....
0>Probe Dimms
1>Probe Dimms
1>Init Mem Controller Regs
0>Init Mem Controller Regs
1>Set JBUS config reg
0>Set JBUS config reg
0>IO-Bridge unit 0 init test            
0>IO-Bridge unit 1 init test            
0>Do PLL reset
0>Setting timing to 9:1 12:1, system frequency 167 MHz, CPU frequency 1503 MHz
0>Soft Power-on RST thru SW
0>PLL Reset.....
0>Init SB
0>Initialize I2C Controller
0>Init CPU
0>Init mmu regs
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0>        Size = 00000000.00100000...
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Scrub Mailbox
0>Timing is 9:1 12:1, sys 167 MHz, CPU 1505 MHz, mem 125 MHz.
0>        UltraSPARC[TM] IIIi, Version 3.4
1>Init CPU
1>        UltraSPARC[TM] IIIi, Version 3.4
1>Init mmu regs
1>Setup L2 Cache
1>L2 Cache Control = 00000000.00f04400
1>        Size = 00000000.00100000...
1>Setup and Enable DMMU
1>Setup DMMU Miss Handler
1>Scrub Mailbox
1>Timing is 9:1 12:1, sys 167 MHz, CPU 1505 MHz, mem 125 MHz.
0>Init Memory.....
0>Probe Dimms
1>Probe Dimms
1>Init Mem Controller Sequence
0>Init Mem Controller Sequence
0>IO-Bridge unit 0 init test            
0>IO-Bridge unit 1 init test            
0>Test Memory.....
0>Select Bank Config
0>Probe and Setup Memory
0>INFO:        2048MB Bank 0, Dimm Type X4
0>INFO:        No memory detected in Bank 1
0>INFO:        No memory detected in Bank 2
0>INFO:        No memory detected in Bank 3
0>
0>Data Bitwalk on Master
0>        Test Bank 0.
0>
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = MB/P0/B0/D0 (Bank 0), Motherboard
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG = Pin 166 failed on MB/P0/B0/D0 (Bank 0), Motherboard
0>END_ERROR

0>
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = CPU0 Memory
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG =
         *** Test Failed!! ***

0>END_ERROR

0>
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = CPU0 Memory
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG = No good memory available on master CPU 0, rolling over to new Master.
0>END_ERROR

1>Soft Power-on RST thru SW
1>OBP->POST Call with %o0=00001000.01014000.
1>Diag level set to MAX.
1>Verbosity level set to MAX.
1>MFG scrpt mode set NORM
1>I/O port set to TTYA.
1>Start Selftest.....
1>CPUs present in system: 0 1
1>Test CPU(s).....
1>Init SB
1>Initialize I2C Controller
1>Init CPU
1>DMMU
1>DMMU TLB DATA RAM Access
1>DMMU TLB TAGS Access
1>IMMU Registers Access
1>IMMU TLB DATA RAM Access
1>IMMU TLB TAGS Access
1>Init mmu regs
1>Setup L2 Cache
1>L2 Cache Control = 00000000.00f04400
1>        Size = 00000000.00100000...
1>L2 Cache Tags Test
1>Scrub and Setup L2 Cache
1>Setup and Enable DMMU
1>Setup DMMU Miss Handler
1>Test  Mailbox
1>Scrub Mailbox
1>CPU Tick and Tick Compare Registers Test
1>CPU Stick and Stick Compare Registers Test
1>Set Timing
1>        UltraSPARC[TM] IIIi, Version 3.4
0>Init CPU
0>        UltraSPARC[TM] IIIi, Version 3.4
0>DMMU
0>DMMU TLB DATA RAM Access
0>DMMU TLB TAGS Access
0>IMMU Registers Access
0>IMMU TLB DATA RAM Access
0>IMMU TLB TAGS Access
0>Init mmu regs
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0>        Size = 00000000.00100000...
0>L2 Cache Tags Test
0>Scrub and Setup L2 Cache
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Test  Mailbox
0>Scrub Mailbox
0>CPU Tick and Tick Compare Registers Test
0>CPU Stick and Stick Compare Registers Test
1>Interrupt Crosscall.....
0>Setup Int Handlers
1>Setup Int Handlers
1>Send Int CPU 0
0>Send Int to Master CPU
1>MB:        Part-Dash-Rev#:  3753484-03-50        Serial#:  1X0GKC
1>CPU0 MB/P0/B0/D0:
1>Part#:  M3 12L2920DZ3-CB3   Serial#:  520238db  Date Code:  0814  Rev#:  3344
1>CPU0 MB/P0/B0/D1:
1>Part#:  M3 12L2920DZ3-CB3   Serial#:  520238de  Date Code:  0814  Rev#:  3344
1>CPU1 MB/P1/B0/D0:
1>Part#:  M3 12L2920DZ3-CB3   Serial#:  5208bfe6  Date Code:  0833  Rev#:  3344
1>CPU1 MB/P1/B0/D1:
1>Part#:  M3 12L2920DZ3-CB3   Serial#:  5208c065  Date Code:  0833  Rev#:  3344
1>Set CPU/System Speed
1>Jumper data = 3a
1>..
1>Send MC Timing CPU 0
1>Init Memory.....
1>Probe Dimms
0>Probe Dimms
0>Init Mem Controller Regs
1>Init Mem Controller Regs
0>Set JBUS config reg
1>Set JBUS config reg
1>IO-Bridge unit 0 init test            
1>IO-Bridge unit 1 init test            
1>Do PLL reset
1>Setting timing to 9:1 12:1, system frequency 167 MHz, CPU frequency 1503 MHz
1>Soft Power-on RST thru SW
1>PLL Reset.....
1>Init SB
1>Initialize I2C Controller
1>Init CPU
1>Init mmu regs
1>Setup L2 Cache
1>L2 Cache Control = 00000000.00f04400
1>        Size = 00000000.00100000...
1>Setup and Enable DMMU
1>Setup DMMU Miss Handler
1>Scrub Mailbox
1>Timing is 9:1 12:1, sys 167 MHz, CPU 1505 MHz, mem 125 MHz.
1>        UltraSPARC[TM] IIIi, Version 3.4
0>Init CPU
0>        UltraSPARC[TM] IIIi, Version 3.4
0>Init mmu regs
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0>        Size = 00000000.00100000...
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Scrub Mailbox
0>Timing is 9:1 12:1, sys 167 MHz, CPU 1505 MHz, mem 125 MHz.
1>Init Memory.....
1>Probe Dimms
0>Probe Dimms
0>Init Mem Controller Sequence
1>Init Mem Controller Sequence
1>IO-Bridge unit 0 init test            
1>IO-Bridge unit 1 init test            
1>Test Memory.....
1>Select Bank Config
1>Probe and Setup Memory
1>INFO:        2048MB Bank 0, Dimm Type X4
1>INFO:        No memory detected in Bank 1
1>INFO:        No memory detected in Bank 2
1>INFO:        No memory detected in Bank 3
1>
1>Data Bitwalk on Master
1>        Test Bank 0.
1>
1>ERROR: TEST = Data Bitwalk on Master
1>H/W under test = MB/P1/B0/D1 (Bank 0), Motherboard
1>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1>MSG = Pin 72 failed on MB/P1/B0/D1 (Bank 0), Motherboard
1>END_ERROR

1>
1>ERROR: TEST = Data Bitwalk on Master
1>H/W under test = MB/P1/B0/D1 (Bank 0), Motherboard
1>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1>MSG = Pin 73 failed on MB/P1/B0/D1 (Bank 0), Motherboard
1>END_ERROR

1>
1>ERROR: TEST = Data Bitwalk on Master
1>H/W under test = MB/P1/B0/D1 (Bank 0), Motherboard
1>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1>MSG = ERROR:        miscompare on mem test!
                Address: 00000010.001b0000
                Expected: 00000000.00000001
                Observed: 00000f00.00000001
1>END_ERROR

1>
1>ERROR: TEST = Data Bitwalk on Master
1>H/W under test = CPU1 Memory
1>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1>MSG =
         *** Test Failed!! ***

1>END_ERROR

1>
1>ERROR: TEST = Data Bitwalk on Master
1>H/W under test = CPU1 Memory
1>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1>MSG = No good memory available on master CPU 1, rolling over to new Master.
1>END_ERROR

1>ERROR:
1>        POST toplevel status has the following failures:
1>                MB/P0/B0/D0 (Bank 0), Motherboard
1>                MB/P1/B0/D1 (Bank 0), Motherboard
1>END_ERROR

1>
1>ERROR:        No good CPUs OR CPUs with good memory left.  Calling debug menu
SC Alert: MB/P0/B0/D0 (Bank 0), Motherboard

ching00086

請大神幫忙看看，是不是內(nèi)存掛了？
  MB/P0/B0/D0 (Bank 0), Motherboard
  MB/P1/B0/D1 (Bank 0), Motherboard

swallowcn

先把內(nèi)存換了試試吧！反正就哪么幾招！

bencyber

內(nèi)存有問題，重新插一下看看